The present invention relates to a digital data buffer, and in particular, to a First In First Out (FIFO) buffer, e.g., for use in synchronizing data communication across an integrated circuit to integrated circuit interconnection.
Semiconductor manufacturing technology continues to yield increasing density and speed of Integrated Circuit (IC) devices. The staggering capability of millions of logic gates per square centimeter of silicon enables mass integration, such as fabricating complete Systems on a Chip (SOC). Unfortunately, often the capability for designing highly integrated systems lags behind the manufacturing capability. The increased complexity compounds the risk associated with debugging and verifying the interfaces between blocks of gates that form the SOC and between IC""s.
One approach to shortening the design cycle time of highly integrated devices is Rapid Silicon Prototyping (RSP), wherein hardware and software are concurrently designed for a custom Application Specific Integrated Circuit (ASIC) or an integrated plurality of ASIC""S. RSP combines methodologies of design reuse, on-chip bus architectures and system integration to substantially improve the ability of designers to create advanced custom ASIC""s and associated system software content faster and with a high probability of success. RSP is based on the premise that it is easier to design a system by xe2x80x9cdeconfiguringxe2x80x9d, i.e., removing blocks from, and xe2x80x9cextendingxe2x80x9d, i.e., adding blocks to, an existing and proven reference design made from reusable components.
Standardized busses allow deconfiguring and extending the reference design by enforcing a standardized interface upon the reusable components. Thus, standardized busses provide many benefits such as reduced risk, improved productivity and reduced time to market associated with RSP. One type of standardized bus often required in a system designed using RSP is for high-bandwidth streaming data, hereinafter referred to as a xe2x80x9ctunnelxe2x80x9d.
Interconnecting different IC""s with a tunnel is complicated by differences between the transmitting IC device and the receiving IC device. For example, the two IC""s may be fabricated using differing fabrication techniques wherein the transmitting IC device is a peripheral device operating at 200 MHz whereas the receiving IC device is a processing device operating at 400 MHz. As another example, due to manufacturing variances, one IC may operate at a slightly different speed than the other. As a further example, due to the software design, one IC design may operate on the streaming data at varying intervals. Thus, for these and other reasons, the tunnel may become a limitation on the throughput of high-bandwidth streaming data due to synchronization problems and limitations on transmission of data per bus cycle.
Synchronization of data in a chip-to-chip interconnection is conventionally provided by a First In First Out (FIFO) circular buffer, also referred to herein as FIFO, in both the transmitting IC device and the receiving IC device. The transmitting FIFO buffers data elements prior to transmission. The receiving FIFO buffers data elements received from transmission. Conventional FIFO circular buffers include a read port and a write port that access a memory array. A write pointer points to an open data slot next to the most recently written to data slot. A read pointer points to the data slot containing the oldest data element stored in the data buffer, next to the data slot last read from the buffer. During each bus cycle to the FIFO, the read port uses the read pointer to successively address the next memory location after each read from the memory array and the write port uses the write pointer to successively address the next memory location after each write to the memory array. Control circuitry is provided to prevent writing to a full FIFO and to prevent reading from an empty FIFO.
Since the FIFO is limited to read and/or to write one data element per bus cycle, the tunnel is often effectively limited to the clock rate of the slower of the two IC devices. For example, a slow transmitting IC device would fill its transmitting FIFO buffer at a corresponding slow rate. A faster receiving IC device with a faster receiving FIFO buffer would tend to empty its buffer more quickly, and essentially be forced to wait for new data to be communicated and placed in its buffer. Thus, the tunnel is band limited to the rate at which the transmitting FIFO is capable of sequencing out its stored data. Alternatively, a fast transmitting IC device would fill its transmitting FIFO buffer faster than a slower receiving IC device and its receiving FIFO buffer could handle it. Thus both buffers would tend to be filled, limited by the rate at which the receiving FIFO buffer could sequence out the received data.
Speeding up a slower IC device in order to have a faster FIFO is often impractical, due to the increased manufacturing costs. Alternatively, adding an additional channel to the tunnel to increase the bandwidth of *n streaming data may be impractical due to limitations on the available number of conductors between IC""s and/or the additional complexity and delay in separating and recombining data transmitted through the separate channels.
Therefore, a need exists for a manner of maximizing the bandwidth of a tunnel coupled to IC""s of differing communication abilities, (e.g., due to differing clock speeds). In particular, a significant need exists for a FIFO buffer that can increase the bandwidth of data elements transferred and thus can assist in harmonizing independent IC""s coupled over a tunnel.
The present invention addresses these and other problems in the prior art by providing a First In First Out (FIFO) buffer capable of unidirectionally transmitting multiple data elements per bus cycle, thereby increasing the amount of data transmitted without increasing bus speed. In addition, a FIFO buffer may also be provided that permits a selectable number of data elements to be unidirectionally transmitted within a given bus cycle, such that the effective bandwidth of the FIFO buffer can be dynamically controlled.
Consistent with one particular aspect of the invention, a FIFO buffer includes a memory array having a plurality of data slots with each data slot storing a data element. FIFO control circuitry responds to a data command by performing either a single data element transfer or a double data element transfer with the memory array.
Consistent with another aspect of the invention a FIFO buffer is used in a communication link between transmitting and receiving devices. The FIFO includes a pair of write ports and a pair of read ports that access data elements from a memory array. FIFO control circuitry is responsive to a write data command to perform either a single or double data element write via the write ports to the memory array. The FIFO control circuitry is also responsive to a read data command to perform either a single or double data element read via the read ports from the memory array.
Consistent with yet a further aspect of the invention, a communication link between transmitting and receiving devices includes a transmission FIFO buffer that transmits data elements to a receiving FIFO buffer across a transmission channel. Each FIFO buffer includes FIFO control circuitry to perform either a single or double data element read in response to a read data command and to perform either a single or double element write in response to a write data command.
Consistent with yet a further aspect of the invention, a method of communicating data elements between transmitting and receiving devices includes responding to a write data command by performing either a single or double data element write and responding to a read data command by performing either a single or double data element read.
Consistent with an additional aspect of the invention, a FIFO buffer includes a plurality of ports for accessing data slots of a memory array and FIFO control circuitry that responds to a data command to unidirectionally access a plurality of data slots via the plurality of ports.
The above and other objects and advantages of the present invention shall be made apparent from the accompanying drawings and the description thereof.